1. Field of the Invention
The present invention relates to liquid crystal display devices. More particularly it relates to reducing electrical shorts in liquid crystal display devices.
2. Background of the Related Art
Significant progress has been made in developing flat panel displays. In particular, liquid crystal display devices (hereinafter abbreviated LCDs) have proven beneficial because of their high contrast ratio, low power consumption, lightweight, and suitability for displaying moving images. Indeed, LCDs have become widely used substitutes for cathode ray tubes.
Generally, an LCD includes a thin film transistor (hereinafter abbreviated TFT) array on a lower substrate, an upper substrate having color filters, and a liquid crystal layer between those substrates. FIG. 1 shows a partial layout of a related art LCD, while FIG. 2 shows a cross-sectional view of that LCD along line I–I′ of FIG. 1. The lower substrate 101 includes gate lines 102 (only one is shown) and data lines 105 (only one is shown) that intersect to form a matrix of unit pixels. A TFT is formed at the gate and data line 102 and 105 crossing. That TFT is formed by stacking a gate electrode 102a, a semiconductor layer 104, a source electrode 105a, and a drain electrode 105b. A pixel electrode 107 in the unit pixel area electrically connects to the drain electrode 105b. 
The lower substrate 101 also includes a storage capacitor comprised of a lower electrode 102c, which is formed simultaneously with the gate line 102, and an upper electrode 105c, which is formed simultaneously with the data line 105. The storage capacitor maintains a voltage during a turn-off interval of the TFT.
The lower substrate 101 is beneficially fabricated by sputtering a low resistance metal layer on the substrate 101, and then by forming a gate pattern comprised of the gate line 102, the gate electrode 102a, and the lower electrode 102c by patterning that metal layer. A gate insulating layer 103 is then formed on the exposed surfaces, including on the gate pattern. The semiconductor layer 104 is then formed on the gate insulating layer 103 and over the gate electrode 102a. 
Then, a data pattern comprised of the data line 105, source/drain electrodes 105a/105b, and the upper electrode 105c is formed by sputtering and patterning a metal layer over the exposed surfaces, including over the semiconductor layer 104. Ideally, except for the desired data pattern, the metal layer is completely removed. However, as shown in FIG. 2, sometimes metal residue 105d remains around the edges of the gate pattern.
The data pattern is beneficially formed by a wet etch process. Wet etching is performed by dipping the substrate 101 in a chemical solution, or by spraying a chemical solution on the substrate, so as to remove metal that is not protected by a photoresist. While generally successful, wet etching has problems. For example, edges of the data pattern can be over etched, or residue 105d can remain.
The residue 105 can electrically short the source electrode 105a and the drain electrode 105b, and/or the upper electrode 105c and the data line 105, together. This is shown in FIG. 1, where the source electrode 105a is electrically connected to the drain electrode 105b through residue 105d, and the upper electrode 105c is connected to a data line 105 through residue 105d′. 
Subsequently, a thick passivation layer (not shown in FIG. 1 or FIG. 2) is formed over the substrate 101, including the data pattern. A pixel electrode 107 is then formed in the pixel area over the passivation layer, and in electrical contact with the drain electrode 105b. 
The residue 105d (and 105d′) can cause device failure. Therefore, a technique of preventing such failures would be beneficial.